Dear Kevin, thanks for the valuable comments. Sorry if I did not reply to you yet. I just need some time to study the solutions and to implement everything. I will come back with results soon.

PS. forgot to say that a larger FIFO into the FPGA would of course help mitigating the issue, but I cannot accept it, due to low-latency requirements. I demand the DMA burst to stay below 16 samples, at most.

PS. forgot to say that a larger FIFO into the FPGA would of course help mitigating the issue, but I cannot accept it, due to low-latency requirements. I demand the DMA burst to stay below 16 samples, at most.

PS. forgot to say that a larger FIFO into the FPGA would of course help mitigating the issue, but I cannot accept it, due to low-latency requirements. I demand the DMA burst to stay below 16 samples, at most.

PS. forgot to say that a larger FIFO into the FPGA would of course help mitigating the issue, but I cannot accept it, due to low-latency requirements. I demand the DMA burst to stay below 16 samples, at most.

PS. forgot to say that a larger FIFO into the FPGA would of course help mitigating the issue, but I cannot accept it, due to latency requirements. I demand the DMA burst to stay below 16 samples, at most.